Why is AEX implemented in SGX if Intel implemented x86 securely?

[ryacko at gmail.com (Ryan Carboni)]

The buried lede in NEMESIS and FORESHADOW:

For the â??case of a fault or external interrupt, the processor executes an
Asynchronous Enclave Exit (AEX) procedure that saves the execution context
securely in a preallocated state save area inside the enclave, and replaces
the CPU registers with a synthetic state to avoid di- rect information
leakage to the untrusted ISR.â??

Seems. Odd.

I dunno. Did anyone read x86 documentation?
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